1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device that performs a repair operation through self-address rupture.
2. Description of the Related Art
A defective memory cell of a semiconductor memory device may be repaired in the wafer or package state. For a repair operation, repair addresses of defective memory cells may be programmed in a fuse unit. Specifically, for a repair operation in the package state, the repair addresses may be programmed in the fuse unit through self-address rupture. In contrast, repair operations n the wafer state are accomplished by external testing equipment. FIG. 1 is a block diagram for illustrating a repair operation through self-address rupture in a typical semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a bank group 110, a test data processing unit 120, a repair address latching unit 130, and a fuse unit 140.
The bank group 110 includes a plurality of memory cell arrays, and outputs a plurality of pieces of test data GIO_DATA<0:N> in a compression test mode. A compression test is used in order to reduce a test time, and is performed by writing substantially the same data in a plurality of memory cells in a write operation, and compressing and outputting data of the plurality of memory cells in a read operation.
The test data processing unit 120 combines the plurality of pieces of test data GIO_DATA<0:N> with one another and outputs a fail detection signal GIO_FAIL when a self-address rupture signal SELF_RUP is received. When all the plurality of pieces of test data GIO_DATA<0:N> do not have substantially the same value, the test data processing unit 120 determines a corresponding bank as a failed bank and generates the fail detection signal GIO_FAIL. The self-address rupture signal SELF_RUP is outputted from a mode register set, and is directly received from outside (e.g. an external piece of testing equipment or a host) of the semiconductor memory device, or is generated inside the semiconductor memory device.
The repair address latching unit 130 latches addresses ADD<0:K> corresponding to the failed bank in response to the fail detection signal GIO_FAIL. When the fail detection signal GIO_FAIL is activated and a bank is determined to have failed, the repair address latching unit 130 stores the addresses ADD<0:K> applied to the repair address latching unit 130. The addresses ADD<0:K> applied to the repair address latching unit 130 correspond to addresses of a bank in which the plurality of pieces of test data GIO_DATA<0:N> have been stored.
The fuse unit 140 includes a fuse set, and electrically programs repair addresses ADD_LAT<0:K> outputted from the repair address latching unit 130 in the fuse set when a rupture enable signal RUP_EN has been activated. The fuse unit 140 receives excess current or high voltage and performs programming work for changing electrical connection states of respective fuses.
FIG. 2 is a detailed circuit diagram of the repair address latching unit 130 illustrated in FIG. 1.
Referring to FIG. 2, the repair address latching unit 130 includes a pass gate PG that is driven in response to the fail detection signal GIO_FAIL, and a latch section 210 that latches the addresses ADD<0:K> depending on whether the pass gate PG is driven.
The pass gate PG selectively transfers the received addresses ADD<0:K> under the control of the fail detection signal GIO_FAIL, and the latch section 210 stores a signal transferred from the pass gate PG.
As described above, in the repair operation through the self-address rupture, it is determined through the plurality of pieces of test data GIO_DATA<0:N> outputted from the bank whether the bank is failed. Addresses corresponding to a bank determined to be failed are stored, and the stored addresses are programmed. In such a repair operation, since it is possible to efficiently detect a repair address through the compression test, repair address programming work is efficiently performed.
In a memory chip used in the mobile field, the bank structure is divided into a first area (left) and a second area (right) other than a single area, and a repair operation is performed. That is, when failure occurs in the first area (left) or the second area (right), a repair operation of a corresponding area is performed. However, when failure simultaneously occurs in the first area (left) and the second area (right), a repair operation of the corresponding areas may not be properly performed due to a collision of information reporting the occurrence of failure.